1) Field of the Invention
This invention relates generally to a semiconductor device having a multi-layered wiring structure and a method of manufacturing the same and more particularly, to a semiconductor device in which different wiring layers are connected to each other by a metal plug in a via and a method of manufacturing the same.
2) Description of the Prior Art
Multi-layer interconnects are important technology in semiconductor manufacturing. Interconnects electrically, connect together different conductive wiring layers in a semiconductor chip. The conductive layers can be layers formed on a substrate surface, such as source/drain contacts or gate structures, or overlying metal wiring layers. It is important that these interconnects, vias, and conductive wiring layers be reliable, be as small as possible to miniaturize the circuit and have wide process windows for high yields.
Conventional processes have at least the following three major problems: (1) via/wiring etch misalignment, (2) voids (dimples) in the tops of the tungsten plugs, and (3) recesses in the barrier layers surrounding tungsten plugs. These problems are explained below.
1) Via Misalignment/Metal Patterning Misalignment Problem
The conventional processes have via misalignment/metal patterning misalignment which leads to shorting and defects. A conventional method of manufacturing a semiconductor device having a multi-layered wiring structure in which respective wiring layers are connected to each other by a via will be described with reference to FIGS. 1A to 1D. As shown in FIG. 1A, a silicon oxide layer 102 is formed on a silicon substrate 100 by a chemical vapor deposition method. A first aluminum layer is deposited on the entire surface of the silicon oxide layer and is patterned to form a first wiring layer 104. Then a thick silicon oxide film 106 is formed over the entire surface of the resultant structure. Subsequently, the silicon oxide film formed over the first wiring layer 104 is removed by an reactive ion etch (RIE) method using a predetermined mask, thereby forming a through-hole (via) 110.
However, as shown in FIG. 1A and in top plan view FIG. 1C, the via 110 may not be formed in the correct position over the metal line 104 due to mask misalignment or process variation. If the via hole 110 deviates from the correct position in this manner, a portion of the silicon oxide film 102 near the wiring layer 104 is etched. In this case a leakage current is produced between the second wiring layer 114 and an underlying polycrystalline silicon wiring layer (not shown) or the silicon substrate 100, or defects such as short circuits occur in the worst case.
As shown in FIGS. 1B and 1C, when the second metal 114 mask/etch is misaligned with respect to the via hole 110, the first wiring layer 104 is mis-etched thus causing a reliability or disconnection defect.
Referring to FIG. 1D, to remedy these two misalignment and etch problems, manufacturers have increased the area of the wiring layers 104114 under the vias 110, but this has increased the size of the chips.
Workers in the art are aware of this first problem of over etching around first level metal contacts (wire layer). For example U.S. Pat. No. 5,286,674 (Roth) shows a method of forming sidewall spacers formed of a dielectric material on the adjacent sides of metal lines so that during formation of a via in the overlying dielectric layer, the sidewall spacers prevent trenching of underlying dielectric layer. The sidewall spacers are formed of an overlying dielectric material. However, this invention could be improved by providing a larger metal plug/wire layer contact area that lowers the contact resistance.
U.S. Pat. No. 5,462,893 (Matsulka) shows a method of improving metal interconnections. Matsulka uses amorphous polysilicon layer 14 as an etch stop on the sidewalls of a first wiring layer. However, this invention could also be improved by providing a larger metal plug/wire layer contact area that lowers the contact resistance.
U.S. Pat. No. 5,451,543 (Woo et al. ) shows a method for making a vertical profile contact opening using an etch stop layer, interposed between a conductive layer and a dielectric layer.
These patents help prevent some of the over etch problems, but further improvement can be made by improving the sidewall spacer, allowing further reduction in the metal line width (e.g., metal contact), and allowing more alignment tolerance for the via etch.
2) W-plug Dimple Recess Problem
A second problem with current processes is the depression (void, or dimple) 107118 formation in the conductive plug as shown in FIGS. 1E and 1G. A contact hole is formed in an insulating layer 106. Next, a barrier metal 132 is formed over the contact hole. The barrier layer is thicker at the top of the contact hole than at the bottom due to the deposition dynamics. A tungsten layer 105 is formed filling the hole and a void (or buried seam) 107 forms because of the barrier layer overhang and the tungsten deposition dynamics. As shown in FIG. 1F, when the tungsten layer is etched back the buried seam is exposed forming a dimple 107. The depth of the dimple 107 can be in the range of between about 500 and 4000 xc3x85 and the overall tungsten plug 105 depth (i.e., the thickness of layer 106) is in the range of between about 8000 and 10,000 xc3x85.
As shown in FIG. 1G, a metal layer 114 and a second tungsten plug 116 are formed over the dimple 107. The dimple 107 is replicated and made deeper in the second tungsten layer forming a second dimple 118. The second dimple 118 has a depth 118A as shown in FIG. 1G. This dimple causes reliability problems.
3) TiN Barrier Recess Problem
A third problem with conventional processes is the barrier layer recess 120 as shown in FIGS. 1H and 1I. As shown in FIG. 1H, a first metal layer 104, a barrier layer 132, and a tungsten plug 105 are formed. Next a second metal layer 116 and a second metal photo resist pattern 117 is formed over the surface. Normal photo process variations can cause the photo resist pattern 117 to be misaligned. During the subsequent etch, the exposed barrier layer 132 will be etched away. As shown in FIG. 1I, a recess 120 is formed. This recess will cause reliability and yield losses.
Therefore, there is a need for an improved interconnect structure and process that can overcome the above three problems. The method/structure is needed that prevents the via misalignment and second metal misalignment etch problems (FIG. 1B), allows further reduction in the metal line (104) width (FIG. 1D), reduces metal contact resistance, and allows more alignment tolerance for the via etch (FIG. 1C). Moreover, the method/structure should alleviate the conductive plug depression (dimple) problem (FIG. 1G) and the barrier layer recess problem (FIG. 1I).
It is an object of the present invention to provide a method and a structure for forming an interconnect structure that electrically connects wiring layers and that reduces wiring width.
It is an object of the present invention to provide a structure and a method for connecting different metal layers without increasing wiring pitch or reducing via tolerances, and for alleviating the conductive plug dimple problem and the barrier layer recess problem.
It is another object of the present invention to provide a structure and a method for a wiring layer that has conductive sidewall spacers and a stacked plug interconnect that fills up depressions (e.g., dimples) in the underlying plug and recesses in the plug barrier layer.
In brief, to accomplish the above objectives, the present invention provides a structure and a method of electrically connecting two wiring layers. The first wire layer is formed over a dielectric layer and a TiN layer is formed over the top of the first wire layer, Next, sidewall spacers composed of titanium nitride and tungsten are formed on the first wire layer sidewalls. An inter metal dielectric (IMM) layer is formed over the surface and a via is etched exposing the first wire layer. A tungsten plug with an outer TiN barrier layer is formed filling the via. On top of the tungsten plug, a second wire layer is formed also having titanium nitride and tungsten sidewall spacers. The titanium nitride/tungsten spacers act as an etch stop for the via etch and also increase the contact area of the first and second wiring layers. The spacers also fill in TiN barrier layer recesses in the tungsten plug and fill in (voids) dimples in the top of the tungsten plug.
In slightly more detail, the method of making a multi-layered semiconductor interconnect device with conductive sidewall etch stoppers and a stacked plug interconnect begins by providing a semiconductor substrate having an overlying insulating layer. Next, a first wiring layer is formed over said substrate insulating layer. First conductive sidewall spacers are formed on the sidewalls of the first wiring layer. An inter metal dielectric layer is formed over the first wiring layer, the first conductive sidewall spacers, and the substrate. A via is etched through the inter metal dielectric layer exposing portions the first wiring layer and portions of the first conductive spacers. The via opening is defined by sidewalls of the inter metal dielectric layer. A plug barrier layer is formed over the inter metal dielectric layer and over the sidewalls of the inter metal dielectric layer. A tungsten plug is formed filling the via opening thereby forming an interconnect.
The invention provides an interconnect structure comprising: a first wiring layer having a predetermined wiring width and a predetermined shape on a semiconductor substrate the first wiring layer having sidewalls; first conductive sidewall spacers formed on the sidewalls of the first wiring layer; an inter metal dielectric layer covering the first wiring layer and the first conductive sidewall spacers; a via in the inter metal dielectric layer over at least a portion of the first conductive sidewall spacers, the via having a width smaller than the total width of the first conductive sidewall spacers and the first wiring layer; a first tungsten plug in the via electrically connected to at least the first conductive spacer; the first tungsten plug having a top, bottom and sides; the first tungsten plug having an outer coating of titanium nitride covering the bottom and sides; a second wiring layer having a predetermined wiring width and a predetermined shape; the second wiring layer over and contacting a portion of the first tungsten plug; the second wiring layer having sidewalls; and second conductive sidewall spacers on the sidewalls of the second wiring layer.
The method of the instant invention reduces the size of the chip by about 30 to 60% over conventional processes by reducing the size of the metal lands and via extensions. The conductive spacers on the first and second wiring layers increase the metal layer contact area providing more via hole tolerance and lowers contact resistance. Second, the invention fills up TiN recesses in the TiN plug barrier layer that surrounds the tungsten plug, thereby forming a more reliable and stable connection between the first and second metal layers. Third, the invention improves connection between the first and second metal layer where the W-plug dimple is filled in with the tungsten with the tungsten spacers is formed. This improves the conductivity and reliability of the interconnection.